An MRAM is a promising nonvolatile memory from a viewpoint of high integration and high-speed operation. In the MRAM, a “magnetoresistance element” that exhibits a magnetoresistance effect such as TMR (Tunnel MagnetoResistance) effect is used as a memory element. The magnetoresistance element includes a non-magnetic layer and two ferromagnetic layers on both sides of the non-magnetic layer. One of the two ferromagnetic layers is a magnetization fixed layer (pinned layer) whose magnetization direction is fixed and the other thereof is a magnetization free layer (free layer) whose magnetization direction is reversible.
A resistance value (R+ΔR) of the magnetoresistance element when the magnetization directions of the magnetization fixed layer and the magnetization free layer are “anti-parallel” to each other is higher than a resistance value (R) when the magnetization directions are “parallel” to each other due to the magnetoresistance effect. A memory cell of the MRAM nonvolatilely memorizes a data by utilizing the change in the resistance value. For example, the high-resistance state is related to data “1” and the low-resistance state is related to data “0”. It is possible to determine the data stored in the memory cell by detecting the resistance value of the magnetoresistance element. On the other hand, it is possible to rewrite the data stored in the memory cell by switching the magnetization direction of the magnetization free layer.
FIG. 1 shows a part of a circuit configuration of an MRAM described in Japanese Laid-Open Patent Application JP-2004-348934. A plurality of write word lines 103W and a plurality of read word lines 103R extend in the X-direction and are connected to an X-selector 108. Moreover, a plurality of first bit lines 104 and a plurality of second bit lines 105 extend in the Y-direction and are connected to a Y-selector 111.
A memory cell array 110 has a plurality of memory cells 120 arranged in an array form. Each memory cell 120 has a transistor 106 and a magnetoresistance element 107. Agate of the transistor 106 is connected to the write word line 103W. One of source/drain of, the transistor 106 is connected to the first bit line 104, and the other thereof is connected to the second bit line 105. One end of the magnetoresistance element 107 is connected to the read word line 103R, and the other end thereof is connected to the second bit line 105.
Some memory cells 120 are reference memory cells 120r. The first bit line 104 and the second bit line 105 connected to the reference memory cell 120r are a first reference bit line 104r and a second reference bit line 105r, respectively. The current sense amplifier 115 is connected to the Y-selector 111 and the second reference bit line 105r. 
Data reading from a certain memory cell 120 (selected memory cell 120s) is as follows. The X-selector 108 selects one read word line 103R connected to the selected memory cell 120s and applies a read voltage to the read word line 103R. The Y-selector 111 selects one second bit line 105 connected to the selected memory cell 120s. A sense current Is flows through the selected second bit line 105 due to a difference between a voltage of the current sense amplifier 115 and a voltage of the read word line 103R. Magnitude of the sense current Is depends on a resistance state of the magnetoresistance element 107 of the selected memory cell 120s. Moreover, a reference current Ir flows through the second reference bit line 105r connected to the reference cell 120r. 
The current sense amplifier 115 determines a data stored in the selected memory cell 120s, based on the sense current Is and the reference current Ir. For example, let us consider a case where the data of the reference cell 120r is fixed to “0”. In this case, if the sense current Is is substantially equal to the reference current Ir, the current sense amplifier 115 determines the data stored in the selected memory cell 120s as “0”. On the other hand, if the sense current Is is smaller than the reference current Ir, the current sense amplifier 115 determines the data stored in the selected memory cell 120s as “1”.
It should be noted here that there exists a current that flows without passing through the selected memory cell 120s. The MRAM shown in FIG. 1 has a cross-point array configuration in which the memory cells 120 are connected through a plenty of parallel paths. At the time of data reading from the selected memory cell 120s, the current that does not pass through the selected memory cell 120s flows on the parallel paths. The current is hereinafter referred to as a “parallel current”. The parallel current affects the sense current Is flowing through the selected second bit line 105. That is, the parallel current causes deterioration in reliability of the data determination for the selected memory cell 120s. In order to enhance reliability of the read data, it is important to suppress the influence of the parallel current.
Japanese Laid-Open Patent Application JP-2002-8369 also describes a cross-point cell array. According to this technique, at the time of data reading, a voltage Vs applied to a selected bit line and a voltage Vns applied to non-selected bit lines are designed to be equal to each other in order to enhance the reliability of read data. However, it is difficult in practice to make the voltage Vs and the voltage Vns exactly the same.